1) Field of Invention
The invention relates to stitching (strapping) methods of forming high-density Metal/polysilicon Oxide Nitride Oxide Silicon (MONOS) memory arrays with reduced bit line resistance, reduced control gate resistance and reduced word gate resistance using three-level metal lines, resulting in high density MONOS memory arrays with high performance.
2) Description of Prior Art and Background
Twin MONOS structures were introduced in the U.S. Pat. No. 6,255,166, and U.S. patent application Ser. Nos. 09/861,489 and 09/595,059 by Seiki Ogura et al. and also various array fabrication methods of the twin MONOS memory array were introduced in U.S. Pat. Nos. 6,177,318 and 6,248,633 B1 and U.S. patent application Ser. No. 09/994,084 filed on Nov. 21, 2001.
The twin ballistic MONOS memory cell, illustrated in FIG. 1A, may be arranged into a bit diffusion array as follows: each memory cell contains two nitride regions 031 which comprise storage elements for one word gate 040, and half a source diffusion and half a bit diffusion (003). The diffusion junctions are shared by two adjacent storage elements. Control gates can be defined separately (042) or shared together (043) over the same diffusion (003). The control gate is electrically isolated from the underlying diffusion junctions. Diffusions are shared between cells and run in parallel to the sidewall control gates (042), and perpendicular to the word line (041). The diffusion lines become bit lines.
In a conventional MOSFET memory, a transistor structure consisting of one polysilicon gate between source and drain diffusions is used and word gate polysilicon line and diffusion bit lines are orthogonally placed. When the memory array gets large, the bit line (BL) and word gate line (WG) become long. The word line resistance due to the series of word gates is high in large memory devices. In order to reduce word line resistance, it is necessary to connect the word line periodically to a metal line that runs in parallel to the poly word lines. This is referred to as a “stitched” or “strapped” word line. Also the bit diffusion line can be sub-arrayed and the bit line can be “stitched” by a conductive metal line. In a typical memory, each polysilicon word line is stitched to a metal word line which runs on top of each poly word line, and each diffusion line, which runs orthogonally to the word lines is stitched by another layer of metal line.
However, in the high-density twin MONOS cell shown in FIG. 1A, the transistor consists of three gates between source and drain diffusions. Three resistive layers of control gate and word gate and bit diffusion may need to be stitched to reduce resistance and to achieve the target performance. For higher density, the polysilicon control gate lines and diffusion bit lines may run in parallel to and on top of each other. If the cell is metal-pitch limited and requires stitching, that means that two additional layers, of metal lines have to run on top of and contact to the two resistive layers. This is a layout and process challenge, as it is not possible to stitch two resistive layers to two respective metal layers when the set of the composite four lines are running on top of each other within the minimum metal pitch.